1. Field of the Invention
The invention relates generally to data processing systems, and more particularly to systems and methods for improving memory access in data processing systems that utilize both a microprocessor mode and a digital signal processor (DSP) mode.
2. Related Art
Even though current computing systems provide far more computing power than computing systems which are only slightly older, they still do not meet the ever-increasing demand for more processing power. This demand remains ahead of current technologies and drives the development of new technologies that will provide even more computing power.
The need for increased computing power has been addressed in many ways. For example, one approach to addressing the need for increased computing power is to develop new manufacturing technologies and transistor-level component designs which allow computer systems to operate at increasing clock speeds. This allows the computer systems to execute increasing numbers of operations in a given amount of time. Another approach is to develop new designs for complex microprocessors which enable the use of correspondingly complex and powerful data processing techniques. Still another approach is to simplify and/or specialize the tasks to be performed by a processor and to fine-tune the operation of the processor to maximize the efficiency with which it performs these specialized tasks.
Each of these approaches to providing increased computing power has its own advantages and disadvantages. For example, one advance that has been made in the area of complex microprocessor design is the use of pipelining. Pipelining is a technique in which a processor operates on multiple instructions concurrently. Pipelining takes advantage of the fact that each instruction executed by the processor is executed in several stages. Consequently, when one instruction has completed a first stage of execution and has moved on to the next stage, a subsequent instruction can begin the first stage of execution, even though the first instruction has not completed execution. Pipelining thereby allows the execution of multiple instructions to overlap and, even though it may take several cycles for a single instruction to be executed, the concurrent execution of multiple instructions can allow one of the instructions to be completed (and execution of another instruction initiated) at each cycle. In other words, the throughput of the processor is increased.
One of the drawbacks of pipelining, however, is that it increases that complexity of the processing of each instruction. For instance, consider execution of a series of program instructions in which a value is computed in a first instruction, and the value is then used to compute a second value in the next instruction. Although this situation does not present a logical problem, it must be remembered that execution of the first instruction will not be complete before execution of the second instruction begins. As a result, the information which is needed for execution of the second instruction is not available when the instruction begins execution. This is referred to as a data hazard. The processor may also encounter control hazards. For instance, if the program branches to an instruction that is identified by the result of the first instruction, the processor does not know which instruction is next until execution of the first instruction is completed. A pipelined microprocessor must be designed to detect and handle data and control hazards in order to ensure proper execution of the program.
Simplified processors have advantages and disadvantages as well. Digital signal processors (DSPs) are often used when it is desired to process large amounts of data in a repetitive fashion. Because the DSP is optimized for a very specific data processing work load that has a high degree of both regularity and parallelism, it can perform data processing functions very quickly and efficiently. On the other hand, the DSP is not optimized for control functions such as instruction scheduling or hazard handling, and performs poorly in comparison to general-purpose microprocessors. Because the DSP is not optimized to handle data hazards or control hazards that can be easily handled by the microprocessor, a programmer must account for any potential hazards in writing the program for the DSP. For instance, the programmer must know how long it takes for data to be retrieved from memory, and must ensure that there is a sufficient delay between a data access and a subsequent instruction that will utilize the data. If the programmer does not avoid these hazards, errors will occur in the execution of the program.
More recently, dual-mode systems that utilize both pipelined processor technology and DSP technology have been developed. These systems may include both a microprocessor core and a DSP core, as well as logic to determine when one or the other should be used to execute program instructions. Alternatively, the systems may utilize a microprocessor that can function either normally (in a microprocessor mode) or in a DSP mode in which hazard detection and control functions are not used. If a group of program instructions to be executed are simple data processing tasks, the DSP core or DSP mode can be selected, and the benefit of high processing speed can be obtained. If the program instructions define more complex tasks and control functions, the microprocessor core or microprocessor mode can be selected to take advantage of the full hazard detection and control capabilities of the microprocessor. These dual-mode systems thereby attempt to gain the best of both (pipelined processor and DSP) worlds.
Because the development of such dual-mode data processing systems is in its early stages, these systems are constructed using supporting components and/or subsystems that were designed for one mode or the other, but not both. For example, memory architectures that are used with these systems are the type that are normally used with pipelined microprocessors. These architectures typically include multiple levels of cache memories to reduce data latencies while still allowing a great deal of flexibility. In these architectures, a first-level (L1) cache has a small amount of memory that can be very quickly accessed, and may have intermediate-level caches (e.g., L2, L3) which have increasing amounts of memory, but also increasing data latencies with each successive level. Finally, there is a main memory which has a great deal of space for data storage, but may have very long data latencies. Typically, a processor making a data access will first attempt to access the L1 cache, then the L2 cache, and so on, finally retrieving the data from the main memory if it is not found in any of the caches.
This multi-level cache architecture is well-suited for use with a pipelined microprocessor because recently used or frequently used data can be accessed very quickly. Generally speaking, the less recently (or frequently) data is used, the greater the data latency with which the data can be accessed. While the flexibility of this type of memory architecture works well with a complex, pipelined microprocessor, it is not well-suited for use with a DSP, or a microprocessor operating in a DSP mode. As noted above, a DSP is not designed to handle data or control hazards, and it is the responsibility of the DSP programmer to account for potential hazards. Consequently, the variable data latencies of these multi-level cache memory architectures present problems for the DSP programmer, who cannot predict the data latencies that will be encountered in executing the DSP program instructions.
It would therefore be desirable to provide systems and methods for enabling data accesses in dual-mode data processors, where the data accesses can be made either with the shortest possible (but variable) latencies, or with fixed, predictable latencies. Further, it would be desirable to provide more data storage than is typically available in an L1 cache, and to have data latencies that are less than the latencies associated with accesses to main memory.